A beautiful, healthy location, and the chance to join a world-leader developing cutting-edge, ultra-low power integrated circuits. Join our client as a Digital IC Design Engineer.
Located in the French-speaking region of Switzerland, our client’s expertise within low power integrated circuit development spans 40 years.
They are now seeking a Digital IC Design Engineer to join their wireless team, and offer a great chance to undertake a challenging role operating in all areas of the ASIC design flow process.
In this role you will:
Have a key role in the development of sensor ICs, taking responsibility for design architecture, RTL design and verification process, using UVM methodology Support the Digital IC Design Lead in the product definition and design execution Interface with remote design teams and interface with the quality, design services, fab, and back-end design groups, analog and software teams Receive support and training, and have the chance to innovate and put your ideas into practice You will need:
A degree (BSc / MSc) in Electronic Engineering or similar A proven background working as a Digital IC Design Engineer, with solid hands-on skills in RTL design - Verilog / SystemVerilog (circa 5-10+ years' experience), and digital-analog integration A good handle on ASIC Verification activities Physical implementation knowledge Excellent communication skills in English (French would be a great plus, but not required) To be eligible to work in Switzerland, either with an EU passport or Swiss visa Previous of experience of ultra-low power RF-SOC or mixed signal products, analog modelling, scripting or the automotive industry will all be beneficial Get in touch today for details: contact Rob Hudson @ IC Resources
Located in the French-speaking region of Switzerland, our client’s expertise within low power integrated circuit development spans 40 years.
They are now seeking a Digital IC Design Engineer to join their wireless team, and offer a great chance to undertake a challenging role operating in all areas of the ASIC design flow process.
In this role you will: